This invention relates to a semiconductor integrated circuit having a functional circuit as a substantive circuit, a selector circuit for connecting a particular point of that circuit to an electrode pad for external connection, and a control circuit for controlling the selector circuit, and more particularly, to a semiconductor integrated circuit which can reduce the chip size by simplifying the control circuit.
Conventionally, in a semiconductor integrated circuit having a complicated circuit such as a logical circuit formed within one chip, after making a semiconductor chip after design, principal points as testing points (hereinafter also called as monitor points) in a functional circuit are connected to electrode pads for external connection so that each circuit portion is tested whether it is normal or not. For doing this, the semiconductor integrated circuit is built, in addition to the substantive functional circuit, with a test circuit forming test line for connecting a monitor point to an electrode pad for external connection, a selector circuit for switching over connections between a test line and a substantive circuit line, and a control circuit for controlling the operation of the selector circuit. The semiconductor integrated circuit provided with such a test circuit like this has electrode pads 12 formed around a circuit section 11 forming an integrated circuit, as its concept diagram of an example of arrangement is shown in FIG. 3(a). In this circuit section 11 is formed with a monitor point 13, as one portion 11a of its one example is shown in FIG. 3(b), a test line 14 for leading the monitor point 13 to an outside, and a selector circuit 16 for selecting between the test line 14 and an line 15 of the substantive circuit, wherein the selector circuit 16 is constituted by a switching element 16a and a NOT circuit 16b for inverting a control signal. Incidentally, 17 is a test control terminal for inputting a control signal for controlling the selector circuit 16.
The control signal for controlling the selector circuit 16 through the test control terminal 17 is formed by a shift register 18 and a latch circuit 19, as shown in FIG. 3(c). The shift register 18 is provided with a data DAT input terminal and a clock CLK signal input terminal, while the latch circuit 19 is provided with a latch enable LE input terminal and a reset signal RST input terminal. This example of the control circuit structured by the shift register 18 and the latch circuit 19 provides many and sequential test outputs by merely applying data in sequence to the circuit shown in FIG. 3(c), i.e., by supplying four terminals of the shift register 18 and the latch circuit 19 with respective signals DAT, CLK, LE and RST, particularly where the circuit is made on a large scale basis to have increased number of monitor points, i.e., outputs for testing. Thus, by increasing the number of the test control terminal 17, the selector circuit 16 can appropriately be controlled on such large-scaled integrated circuit.
As stated before, in the test circuit of the conventional semiconductor integrated circuit, a shift register and a latch circuit are used to cope with increase of integration scale in semiconductor integrated circuits. In such cases, however, the four control-signal input terminals, a shift register, and a latch circuit are requisite for conducting a test. To this end, there is a problem that the chip area for a semiconductor integrated circuit increases to leave a cause of cost rising.
Furthermore, these control-signal input terminals or the circuits are portions having no bearing on a user side who utilize a semiconductor integrated circuit. Nevertheless, these portions result in increase in chip area. A problem also lies in that the presence of such test control terminals is inconvenient in packaging and mounting of a semiconductor integrated circuit.